#Sample manager sample rate conversion series#

But this would mean processing large amounts of data with its own penalty in external digital host interface design complexity and power. The greater the number of samples in the digital data, the more accurate the representation of the analog input.

One of the major performance parameters for any ADC application that drives digital data sample rate selection is the accuracy expected from the ADC. Pairing ASRC with a CTSD ADC offers the best of both worlds, simplifying the signal chain design not only on the analog input side but also on the digital output side of the ADC. Next we introduce the novel asynchronous sample rate conversion (ASRC), which can be paired with any ADC architecture to get any desired output sample rate and simplify the digital interface design with the external digital host. We follow up with a quick recap of traditional sample rate conversion techniques in known ADC architectures and their shortcomings. This article starts with an overview of sample rate requirements in various applications and establishes the need for an ADC to support a wide range of output sample rates. A sample rate converter maps the ADC data at the input sample rate to the desired output sample rate. Each application requires a unique digital output sample rate.

The sample rate at which an application requires the digital data for further processing needn’t necessarily be the sample rate at which the ADC samples the analog signal. The job of an ADC is to sample the analog input signal and convert it into an equivalent digitized format. This article introduces a novel on-chip sample rate conversion technique used on a core ADC’s output, allowing signal chain designers to process the ADC digital output data at the desired sample rate for their application. However, there are varied requirements on the sample rate that are different for each application. Digital data output sample rate is a key parameter of an ADC signal chain for any application. We now look at simple, innovative ways of interfacing the ADC data to the external digital host performing application-related processing on this data.

#Sample manager sample rate conversion series#

The article series has highlighted the architectural traits of continuous-time sigma-delta (CTSD) analog-to-digital converter (ADC) modulator loops that simplify the signal chain design on the analog input side of the ADC. CTSD Precision ADCs- Part 5: Digital Data Interface Simplification with Asynchronous Sample Rate Conversion (ASRC)